1. Field of the Invention
The present invention relates to a 1-chip microcomputer and, in particular, to a chip referred to as an evaluation or test chip which is used for evaluating or testing a program built into a 1-chip microcomputer to be mass-produced.
2. Description of the Related Art
Microcomputers have been used for controlling the operations of various industrial equipment and consumer appliances. Generally, the microcomputer for these applications is a 1-chip microcomputer in which devices including logic circuits and memory devices are integrated on a single semiconductor chip. Such a 1-chip microcomputer includes a ROM (Read Only Memory) for storing a program under which the operation of the microcomputer is controlled. The program is developed according to the functions provided for the equipment and so forth, therefore, it is different for each user of the 1-chip microcomputer. Unless an EPROM (Erasable Programmable ROM) is employed in a 1-chip microcomputer, the program must be completely debugged and subjected to functional tests in advance, since it can not be modified once it is written into the ROM.
It is necessary that the functional tests must be performed in a comprehensive system environment including the 1-chip microcomputer and the controlled equipment therefore, the evaluation or test chip is prepared in advance. The evaluation chip is usually fabricated based on the design of a 1-chip microcomputer to be mass-produced, where an external memory device is used as a substitute for the ROM for permanently storing the program. Thus, the program can be subjected to modifications as many times as is required according to the results of the functional tests. To provide access to the external memory device, the evaluation chip is provided with an interface circuit including an address output buffer and data input buffer. The configuration of a conventional evaluation chip will be explained in the following discussion in comparison with that of a chip of the corresponding 1-chip microcomputer to be mass-produced.
FIG. 1 is a schematic plan view of an exemplary arrangement of circuits formed in a chip 20 of a 1-chip microcomputer, the circuits include a RAM (Random Access Memory), registers REG, logic circuits LOGIC, a clock generator CLK, an instruction programmable logic array IPLA, a program counter PC and a ROM. When the ROM receives an address signal from the program counter PC, the ROM outputs corresponding data or an instruction stored therein to the logic array IPLA. In FIG. 1, these circuits are represented as the respective regions set aside for them on the chip 20 in FIG. 1 and will be represented so in the following drawings. Also in FIG. 1, only the connections 22 and 23 relevant to the respective transmission of the address and data signals are illustrated. Generally, the data consists of eight bits in parallel, but the number of the address bits differs depending on the capacity of the ROM; 10 bits for a ROM of 1K bits, for instance. Further, a number of bonding pads 21, which are referred to as first bonding pads hereinafter, are formed at the periphery of the chip 20. The first bonding pads 21 are usually arranged in an array surrounding the circuits. Each of the first bonding pads 21 is connected to one of the circuits with corresponding wiring (not shown). The first bonding pads 21 are disposed at a constant pitch due to the general requirement for automatic bonding machines.
FIG. 2 is a schematic plan view of an exemplary configuration of a conventional evaluation chip for the 1-chip microcomputer shown in FIG. 1. Referring to FIG. 2, the evaluation chip 30 has an extended area around an inner area indicated by a dot-dash line. The inner area is referred to as a device area hereinafter, in which circuits the same as in the 1-chip microcomputer of FIG. 1, except for the ROM, are formed. The arrangement of these circuits in the device area is substantially the same as in the 1-chip microcomputer shown in FIG. 1. The bonding pads 31 corresponding to the first bonding pads 21 in FIG. 1 are formed in the extended area instead of in the device area and are connected to the facilities via not-shown wiring lines. In the evaluation chip 30, the region set aside for the ROM of the 1-chip microcomputer is blank, and an address output buffer 34 and a data input buffer 35 are provided in the extended area of the chip 30 instead. The region 36 is referred to as a ROM region hereinafter. The address output buffer 34 and data input buffer 35 are connected to the PC and the IPLA, respectively, via the respective wiring lines 32 and 33 and allow the evaluation chip to have access to an external memory device for storing the program to be evaluated.
Thus, the masks for fabricating the evaluation chip can be produced based on the existing masks prepared for the mass-production chips of the 1-chip microcomputer, where the required additions include patterns necessary for forming the buffers 34 and 35 and the wirings 32 and 33 added to respective corresponding ones of the existing masks and which provide some modifications in the arrangement of the bonding pads 31 and the connections between the bonding pads 31 and the circuits in the device region.
It is necessary that the circuits in the evaluation chip be tested and found good prior to the evaluation of the program. This requirement is satisfied in an evaluation chip of a 1-chip microcomputer which has already been used in the field. However, when a 1-chip microcomputer is newly developed, either one of a preliminary mass-production chip or an evaluation chip is fabricated in advance for the purpose of the confirmation testing. In other words, if either chip has been fabricated, the development of the other chip can be carried out based on the design of the previous chip.
Referring to FIG. 1, since the ROM has no external connections, no spare bonding pads occur because of the omission of the ROM in the evaluation chip 30. As a result, in FIG. 2, the bonding pads 31 include incremental or additional pads 310 for connecting the buffers 34 and 35 to the external memory device (not shown). The total number of the incremental bonding pads 310 is 18, for example. To accommodate the additional patterns for the incremental bonding pads and the address output and data input buffers, the evaluation chip 30 is generally designed to have an extended area compared with the mass-production chip of FIG. 1.
As described before, the circuits formed in the device area are arranged and interconnected with each other substantially in the same way as in the 1-chip microcomputer shown in FIG. 1. However, the pads 31 and 310 must be disposed with a constant pitch because of the reason mentioned above. Therefore, when the total number of bonding pads 31 is increased due to the addition of the incremental pads 310, the relative arrangement of the pads 31 to the circuits can not remain as in the production 1-chip microcomputer. This means that the modification in the masks for fabricating the conventional evaluation chip is not limited to the addition of the buffers 34 and 35 together with the incremental bonding pads 310 and wiring lines 32 and 33, but involves a comprehensive redesign in of the wiring pattern for connecting the bonding pads 31 to the circuits.
Such a redesign for the number of complicated wiring lines necessary inevitably results in a time consuming procedure and can cause an erroneous connection which makes not only the evaluation chip but the wiring masks useless. Moreover, the conventional evaluation chip must be designed to have a margin for the chip area thereof so as to permit the wirings 32 and 33 to be distributed without intersecting the existing wirings. When the margin is already provided in the mass-production chips, the chip area utilization efficiency is decreased. On the other hand, when the layout in the mass-production chip is optimized and the margin must be afforded in the evaluation chip, the redesign in the wiring pattern inevitably becomes further complicated.